1. Field of the Invention
This invention relates to the formation of integrated circuit structures. More particularly this invention relates to a process for accurately forming narrow dimension structures such as metal lines or gate electrodes of integrated circuit structures on semiconductor substrates.
2. Description of the Related Art
In the accurate formation of fine dimension structures such as, for example, 0.25 micrometer (.mu.m) wide gate electrodes or metal lines in a layer of patternable material, forming a portion of an integrated circuit structure on a semiconductor substrate, a layer of photoresist is first formed over the layer to be etched. The photoresist layer is then exposed to a light pattern through a reticle (light mask). Using a positive mask system, the light exposes those portions of the photoresist layer to be removed. When the exposed photoresist layer is then developed to remove the light-exposed photoresist, a pattern of photoresist (photoresist mask) remains conforming to the desired pattern to be formed in the underlying layer of patternable material, using the photoresist mask as an etch mask.
Conventionally before etching the underlying patternable layer (such as a polysilicon or metal layer) through the resulting photoresist mask, the dimensions of the resulting resist mask are measured to determine the accuracy of the resist mask, since this will determine the accuracy of the desired dimensions in the patternable layer of material to be etched. When the mask is measured and any dimensions are found to be out of specifications, particularly critical dimensions such as the width of the gate electrode or of the metal line, the structure must be reworked by removing the remaining portions of the resist mask, and then starting over again with a fresh layer of photoresist from which a new photoresist etch mask will be formed.
Typically the photoresist mask formation is carried out in a different chamber or apparatus than the apparatus used to measure the critical dimensions of the resulting photoresist mask, so it is not unusual for the measurement step to be carried out on a sampling basis. However, if the critical mask dimensions are not within specifications, e.g., if the mask dimensions on a substrate not measured are incorrect, the subsequent etch pattern etched into the underlying patternable layer, e.g., an underlying polysilicon or metal layer, will also be wrong, resulting in the need to either remove the underlying patterned layer (when possible) or to discard the entire wafer.
It would, therefore, be desirable to provide a process wherein more accurate control of the critical dimensions of resist masks can be maintained and the need for the reworking of resist masks formed out of specification can be either reduced or eliminated. It is further desirable that such a process be carried out on all substrates (rather than only on random samples) to eliminate the problem of underlying patternable layers etched to unacceptable dimensions.